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SmartSwitch
LCD 36 x 24 Pushbutton
LCD SPECIFICATIONS
Characteristics of Display
Display Operation Mode
Display Condition
Viewing Angle
Driving Method
Viewing Area
Pixel Format
Pixel Size
Backlight LED
Absolute Maximum Ratings (Temperature at 25°C)
STN positive, STN negative, FSTN positive
Transflective with built-in LED backlight
Adjustable
1/24 duty. 1/5 bias (built-in driving circuit)
15.0mm x 10.8mm (horizontal x vertical)
36 x 24 pixels (horizontal x vertical)
0.36mm x 0.36mm (horizontal x vertical)
Single color: yellow, white
Bicolor: red/green, yellow/green, yellow/blue
RGB: red/green/blue
Recommended Operating Conditions (Temperature at 25°C)
TM
Items
Symbols
Ratings
Items
Symbols Minimum
Typical
Maximum
Supply Voltage for Logics
Supply Voltage for LCD
Input Voltage
Output Voltage
V DD
V LC
V I
V O
–0.3V to +7.0V
–0.3V to +12.0V
–0.3V to V D D +0.3V
–0.3V to V D D +0.3V
Supply Voltage for Logics
Supply Voltage Yellow
Supply Voltage Blue
Supply Voltage Black/White
Input Voltage
Driving Frequency
V DD
V LC
V LC
V LC
V I
f FLM
4.5V
––
––
––
0V
––
5.0V
7.4V
7.5V
7.3V
––
64Hz: yellow/blue
150Hz: black/white
5.5V
––
––
––
V DD
––
E
DC Characteristics of LCD Drive (Temperature at 0°C to 40°C and V DD = 5.0V ±10%)
Items
Symbols
Test Conditions
Minimum
Typical
Maximum
Unit
High Level Input Voltage
Low Level Input Voltage
High Level Input Leakage Current
Low Level Input Leakage Current
V IH
V I L
I LI H
I LIL
V I = V D D
V I = 0V
0.7V DD
0
V D D
0.3V D D
10
–10
V
V
μA
μA
High Level Output Voltage
Low Level Output Voltage
High Level Output Leakage Current
Low Level Output Leakage Current
Supply Current
V OH
V OL
I LO H
I LO L
I D D
I O H = –500μA
I O L = 500μA
V O = V D D
V O = 0V
f S CP = 1.0MHz
V DD –0.5
0.5
10
–10
500
V
V
μA
μA
μA
LCD Drive Current
I LC
f L P = 2.4kHz V LC = 7.3V ~ 7.5V
500
2,000
μA
Timing Characteristics of LCD Drive IC
Timing Diagram
(Temperature at 0°C to 40°C an d V DD = 5.0V ±10%)
Items Symbols Minimum
Clock Operation Frequency f SCP
Latch Pulse Frequency f LP
Clock High Level Pulse Width t C WH 70ns
Clock Low Level Pulse Width t C WL 70ns
Data Setup Time t DS D 45ns
Data Hold Time t D H D 50ns
Data Output Delay Time
t PD O
Latch Setup Time
t DS L
50ns
Maximum
6.0MHz
50kHz
25ns
SCP
Din
Dout
LP
t r
t CW H t CWL
t DSD
t DHD
t PDO
t f
*1
t DSL
*3
t r
t LWH
*2
t DHL
t f
Latch Hold Time
Latch High Level Width
FLM Setup Time
FLM Hold Time
SCP, LP Rise/Fall Time
t D H L
t LW H
t DS F
t D H F
t r /t f
50ns
200ns
50ns
50ns
15ns
FLM
t DSF
*1 Last data on first line
*2 Beginning data on second line
*3 Location of LP signal on first line
t DHF
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